A flash memory includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, a drain, a floating gate and a control gate. Various voltages are applied to the control gate to program the transistor memory cell with a binary 1 or 0, to erase all of the transistor memory cells as a memory block, to read the transistor memory cell, to verify that the transistor memory cell is erased or to verify that the transistor memory cell is not over-erased.
The undesirable effect of the leakage current from the over-erased transistor memory cells is described as follows. In a typical flash memory, the drains of a large number of transistor memory cells, for example 512 transistor memory cells are connected to each bit line. If a substantial number of transistor memory cells on the bit line are drawing background leakage current, the total leakage current on the bit line may exceed the cell read current. This makes it impossible to read the state of any transistor memory cell on the bit line, and therefore renders the flash memory inoperative.
To overcome the above problems, the over-erased correcting and verifying process and the post over-erased correcting and verifying process are performed on the transistor memory cells, such that the bit line leakage current of the over-erased transistor memory cell can be cured. However, some of the erased transistor memory cell may change to the under-erased transistor memory cell after the over-erased correcting and verifying process and the post over-erased correcting and verifying process are performed.
Referring to FIG. 1, FIG. 1 is flow chart of a conventional erasing method. The conventional erasing method is used to make the under-erased transistor memory cell be erased by performing step S15 after the over-erased correcting and verifying process and the post over-erased correcting and verifying process are performed. The conventional erasing method is executed in a flash memory which comprises a memory management apparatus and a memory module, wherein the memory module comprises a plurality of memory blocks, and each of the memory blocks comprises a plurality of transistor memory cells.
In FIG. 1, at step S11, the memory management apparatus verifies and pre-programs all transistor memory cells of the memory module. Next, at step S12, the memory management apparatus verifies and erases all of the transistor memory cells as a memory block, and that is, the erasing unit is one memory block. It is noted that, in the conventional erasing method, two erasing and verifying processes are performed, wherein step S11 is the first erasing and verifying process while step S15 is the second erasing and verifying process.
Next, to prevent the leakage current of the over-erased transistor memory cell from rendering the flash memory inoperative, at step S13, the memory management apparatus verifies all transistor memory cells of the memory module and performs the over-erased correction (OEC) on the over-erased transistor memory cell(s) of the memory module while the verification result shows at least one over-erased transistor memory cell exists in the memory block. Next, at step S14, the memory management apparatus performs the post over-erased correcting and verifying process to the transistor memory cells of the memory module.
Then, step S15 is executed, the memory management apparatus verifies and erases all of the transistor memory cells as a memory block, so as to correct the threshold voltage of the under-erased transistor memory cell(s) after the over-erased correcting and verifying process and the post over-erased correcting and verifying process are performed, and to make the under-erased transistor memory cells be erased. It is noted that, if the verification result of step S15 shows the memory block should not be erased (i.e. the memory block is not erased), the conventional erasing method is terminated; otherwise (i.e. the memory block is erased), step S13 through S15 are executed again.
Though the threshold voltage of the under-erased transistor memory cell(s) can be corrected after the over-erased correcting and verifying process and the post over-erased correcting and verifying process are performed, the do-loop of the conventional erasing method may be required, and erasing time of step S15 may be required before and after cycling, thus making the conventional erasing method extremely time-consuming.
To reduce the execution time of the conventional erasing method, another one convention erasing method is proposed. Referring to FIG. 2, FIG. 2 is flow chart of a conventional erasing method. The conventional erasing method of FIG. 2 is executed in a flash memory as mentioned above, in particular, an OEC flag is used to determine whether the erasing and verifying process should be performed again.
At step 521, the memory management apparatus verifies and pre-programs all transistor memory cells of the memory module. Next, at step S22, an erasing and verifying process and an over-erased correcting and verifying process are performed by the memory management apparatus, and the OEC flag is used to determine whether to perform the erasing and verifying process again, such that the threshold voltage of the under-erased transistor memory cell(s) can be corrected after the over-erased correcting and verifying process is performed. Next, at step S23, the memory management apparatus performs the post over-erased correcting and verifying process to the transistor memory cells of the memory module, and then the conventional erasing method is terminated.
Step S22 comprises steps S221 through S224, and details of steps S221 through S224 are illustrated as follows. At step S221, the memory management apparatus verifies and erases all of the transistor memory cells as a memory block, and specifically, if the verification result shows the memory block should be erased, the memory management apparatus make at least one erase pulse injected to the transistor memory cells of the memory block for the objective of erasing. At step S221, if the memory block is erased, the memory management apparatus sets an erasing flag (hereinafter, abbreviated as “ERS flag”) to be logically true (i.e. value of “1”). Next, at step S222, the memory management apparatus checks the value of the ERS flag. If the ERS flag is logically true, step S223 is then executed; otherwise (i.e. ERS flag is logically false or “0”), step S23 is then executed.
At step S223, the memory management apparatus verifies all transistor memory cells of the memory module and performs the OEC on the over-erased transistor memory cell(s) of the memory module by executing at least one OEC pulse (i.e. injecting the OEC pulse to the transistor memory cells) while the verification result shows at least one over-erased transistor memory cell exists in the memory block. At step S223, the memory management apparatus sets the OEC flag to be logically true (i.e. value of “1”) if the OEC is performed on the memory block. Next, at step S224, the memory management apparatus checks the value of the OEC flag. If the OEC flag is logically true, step S221 is then executed again; otherwise (i.e. OEC flag is logically false or “0”), step S23 is then executed.
By using the OEC flag, the conventional erasing method of FIG. 2 can save erasing time before cycling (i.e. whether to executed step S221 is determined by the OEC flag). However, the do-loop between the erasing and verifying process (step S221) and the over-erased correcting and verifying process (step S223) may be still required, and the execution time of the conventional erasing method of FIG. 2 is not shortened sufficiently.